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ECC and Signal Processing Technology for Solid State Drives and Multi-bit per cell NAND Flash Memories 2nd Edition

Report No. FI-NFL-FSP-0112, January 2012

In December 2011, it was widely reported that Apple had acquired Anobit Technologies for half a billion dollars. What prompted Apple to spend that kind of money on a five year old startup? As the biggest consumer of NAND flash memories, this was clearly a strategic acquisition. The tie-up follows a less widely known acquisition of Storage Genetics by Micron Technology in 2010. Both Anobit and Storage Genetics were developing advanced ECC and signal processing technologies.

As bit errors increase as NAND flash memory scales below 2xnm process technology and transitions to 3-bit per cell architectures, traditional error correction codes such as BCH, RS and Hamming code will no longer be sufficient. These codes suffer from increased overhead in terms of coding redundancy and read latency as the number of errors corrected increases. In addition, the number of electrons stored in the memory cell is decreasing with each generation of flash memory resulting in reduced signal/noise requiring enhanced sensing techniques.

Digital signal processing technology has been employed in the magnetic recording industry since the early 1990ís when partial-response maximum-likelihood technology (PRML) was commercialized. DSP technology is now being deployed in 3-bit per cell NAND flash memories and a concerted effort is being made by NAND flash manufacturers and a handful of startups to employ digital signal processing technology to improve the endurance and performance of next generation NAND flash memories and solid state drives. Signal processing technology will be essential for the continued scaling of NAND flash memories. .

This research report examines the current state of ECC techniques and explores the technology, roadmap, market, cost and as well as the key players and startups in the flash signal processing space.

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