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ECC and Signal Processing Technology for Solid State Drives and Multi-bit per cell NAND Flash Memories
Report No. FI-NFL-FSP-0110 January 2010
Bit errors are becoming more severe as NAND flash memory scales below 40nm process technology and
transitions to 3-bit and 4-bit per cell architectures. Increased ECC requirements will be required, however,
traditional error correction codes such as BCH, RS and Hamming code suffer from increased overhead in terms of
coding redundancy and read latency as the number of errors corrected increases. In addition, the number of electrons
stored in the memory cell is decreasing with each generation of flash memory resulting in reduced signal/noise
requiring enhanced sensing techniques.
Digital signal processing technology has been employed in the magnetic recording industry since the early 1990’s
when partial-response maximum-likelihood technology (PRML) was commercialized. DSP technology is now being deployed
in 3-bit per cell and 4-bit per cell NAND flash memories and a concerted effort is being made by NAND flash
manufacturers and a variety of startups to employ digital signal processing technology to improve the endurance and
performance of next generation NAND flash memories and solid state drives. Signal processing technology will be
essential for the continued scaling of NAND flash memories.
This research report examines the current state of ECC methods and explores the technology, roadmap, market, cost
and competitive landscape in the flash signal processing space.
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