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Emerging Memory Technologies

Report No. FI-NVM-EMT-1209 December, 2009


Sometime in the next decade, both DRAM and flash memories are expected to face fundamental scaling limitations.

In DRAM, new device structures will be required to overcome short channel effects and junction leakage in the array transistor. In order to maintain the capacitor capacitance of 25fF, high aspect ratio structures and new high-k materials will be required as DRAM scales to 30nm.

NOR flash memory faces challenges in channel length scaling and maintaining the drain bias voltage margin necessary to minimize program disturb.

Electrostatic interference between adjacent cells in NAND flash is becoming a serious issue. As geometries shrink, it becomes much more difficult for the ONO dielectric to wrap around the floating gate to maintain the coupling ratio between the control gate and floating gate. Low-k materials between the cells and high-k materials in the cell will be required for future generations of NAND flash.

As a consequence, DRAM and flash memory vendors are actively researching alternative memory technologies to ensure the continuation of Moore’s Law. Technologies such as floating body cell memory and spin-torque MRAM offer the promise of non-volatile RAM-like performance.

Various technologies including phase change memory, charge trap memory, nanocrystal memory, PMC, RRAM and 3D memory are potential candidates to replace flash memory.

Emerging Memory Technologies provides an overview of the challenges facing emerging memory technologies as well as an analysis of the most likely memories to be commercialized in the next five years.



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